Senior Design Verification Engineer
- Work as part of verification team with responsibility of design verification.
- At IP or module level verification, responsible for all aspects of functional verification of one or multiple blocks.
- At system level Verification, responsible for parts of system verification, to check system level connections and co-operations.
- Develop micro-architectural checkers and coverage components for the block to be verified as part of test plan execution.
- Own and debug failures in simulation to root-cause problems.
- Closely working with RTL engineers of block being verified for test plan development, execution, and debug.
- RTL design experience, Synthesis, static timing closure, formal verification, gate level simulations & block level function verification.
- VMM and systemC experience is desirable.
- Knowledge of scripting languages such as Perl, Tcl and UNIX shell etc is desirable.
- Design knowledge of one/more industry standard bus interfaces (SATA, SPI, HDMI, USB, AMBA etc; ) and memory interfaces (DDR2, DDR3 etc;) will be a good plus.
- Experience of 2D/3D graphics or video post processing will be a good plus.
- Memory system design experience will be a good plus.
- Understanding of board level design issues and debug will be a good plus.