In this role you will implement, model and verify a high speed DDR physical layer interface for our next generation products. The candidate must have strong knowledge of high-speed chip design in both digital logic and circuit aspects. The candidate is ideally an expert in the DDR interface and DRAM technology and has demonstrated experience on DDR3 starting from definition to successful silicon characterization and production. Must have good knowledge and experience working with verification test benches and working collaboratively to verify correct logical functionality. Having knowledge of high speed SERDES, PLL, high speed IO, and packaging is a BIG plus. Needs good understanding of power distribution issues in I/O designs, integration & internal/external timing closure using static timing analysis tools and SPICE. Knowledge of ASIC design flows is a plus. The candidate should possess high motivation & good team work.
Essential Duties and Responsibilities Include: