Design for test (DFT) Architect

Requirements:
BSEE or equivalent with 10+ years of experience in design for test
Demonstrated expertise in structural test, BIST, functional test, and other test/coverage methodologies
Experience and knowledge of RTL design using Verilog
Experience and knowledge of functional verification, especially of DFt features
Experience and knowledge of test pattern generation (both functional and structural)
Experience and knowledge of high-volume test equipment (ATE) and methods (e.g, system functional testing)
 Demonstrated leadership, influencing and communications skills

Description:
Contributes as a DFT architect as part of a world class leading edge processor design team. This challenging position is to work with architecture, implementation and operations to effect high test quality(high fault coverage, low DPM) with low test cost. This position would be the in house expert on scan, BIST, functional patterns, jtag, and SERDES testing. In addition to standard cells, our products have full custom digital logic, analog IO/SERDES, rams, and cams. This leads to a wide breadth of testing scenarios sometimes beyond what commercially available tools can support. Experience with Verilog, scan and functional patterns a must. Proficiency with C++ and scripting languages strongly desired.