Senior CAD Engineer
- Maintain and support Place and Route flow that will be used to design next generation high-performance processor chips. A significant amount of tool customization is required for our semi-custom and full-custom design environments.
- Work with the RTL team in helping them take their blocks (coded in Verilog) through the Place and Route Flow and generating back-end views that meet timing requirements.
- Work with the Physical Verification team in integrating these blocks with minimal issues.
- Work with the Global timing team in debugging/resolving any block level timing issues seen at full chip.
- BS in EE with 6+ years of related experience, or MS with 4+ years of related experience.??
- Experience with industry standard EDA tools for place-and-route, global timing is required.
- Basic understanding of the following concepts is required: clock skew, variation, power optimization, EM, IR, and DFM.
- Strong scripting skills are required (PERL, TCL, UNIX shell etc.).
- Good understanding of hardware description language such as Verilog is a plus.
- Experience in interfacing with RTL and Physical verification teams is a plus.
- Hands on experience for all aspects of chip development process with proficiency in back end design tools and methodologies is a plus.
- Must have effective interpersonal, teamwork, and communication skills.
- Demonstrate good analysis and problem-solving skills.
- Have an inherent sense of urgency and accountability.
- Must demonstrate initiative and a bias for thoughtful action.
- Grounded, detail-oriented, always back up ideas with facts.
- Must Consulting CAD Engineer have the ability to multi-task in a fast paced environment.