Principle ASIC Engineer
Perform ASIC design for large, complex, high-speed ASICs.
- Develop the architecture and micro-architecture of high-speed networking ASICs.
- Implement the design in Verilog or System Verilog.
- Synthesize the design using Synopsys Design Compiler.
- Work with the Physical Design team to optimize the physical design layout and fix timing issues.
- Work with the Verification team to verify your block.
- Show leadership and provide guidance to junior engineers.
- Requires a BS/MS EE or equivalent.
- 10 years of industry experience.
- Strong Verilog or System Verilog skills.
- Strong System C or C/C++ and Perl/shell scripts skills.
- Knowledge of Synopsys Design Compiler is highly desirable.
- Must have good leadership/communication skills.
- Networking experience is highly desirable, but not required.